Superskalar processor is a term for a processor that can perform many
instruction each cycle, using a technique called
pipelining.
For example, the instruction
Add R1, R2, R3
which will add the contents of registers R1 and R2 and place the amount in
register R3. The contents of registers R1 and R2 will initially be transferred to Unit
arithmetic and logic. After the addition of surgery performed, the sum
will be transferred to the register R3. The processor can read the instructions
The next from memory, while the addition of surgery performed. Then if
The instruction also uses the ALU, its operands can be transferred to the input
ALU at the same time with the Add instruction is transferred to the register R3.
In the ideal case, if all instructions are stacked to the maximum degree
may be done, then the execution dilanjutnkan at speeds of completion
instruction in each processor cycle rate. Individualized instruction, may still be
require several cycles of beats to complete. But for the purposes
calculations, the processor superskalar generally able to do in each cycle.
Superskalar processors generally use multiple functional units, creating
parallel pathways in which many different instructions can be executed in
parallel. With these settings, it is possible to start the execution
multiple instructions in parallel per cycle rate. Of course, the parallel execution
logikan program must maintain truth, so that the results obtained
should be equal to the result of a serial execution.
Intel x86 processors that use Intel's architecture is a family superskalar
Pentium, Intel Pentium Pro, Intel Pentium II, Intel Pentium III, Intel Itanium,
Intel Xeon, Intel Pentium 4, Intel Pentium M, Intel Core from Intel Corporation;
family of AMD K5, AMD K6, AMD Athlon, AMD Athlon 64 and AMD Opteron.Nuvola apps mycomputer.png article stubs this computer is a
stub. You can help Wikipedia by expanding it.
Superscalar (superskalar) is a processor architecture that allows the execution
the same time (parallel) of a lot on stage instruction pipeline
as well as other pipeline stages.
Is one of the design to increase the CPU speed. Most of
computer is currently using this superscalar mechanism. Standard pipeline
is used for mathematical processing of integer numbers (integers,
numbers that have no fractional), most of the CPU also has the ability
for processing for floating point data (number berkoma). Pipeline which
integer processing can also be used to process floating point data type
This, however, for certain applications, especially for scientific purposes the application CPU
which has a floating point processing capabilities can improve the speed
the process dramatically.
Superscalar is able menjlankan Instruction level parallelism with a single
the processor. Can be applied in superscalar RISC and CISC, but in general
RISC.
Interesting events that can be done with this method is in a superscalar
estimate the branching instruction (brach prediction) and the approximate
execution orders (speculative execution). This event is very beneficial
create a program that requires a bifurcation of the instruction that
dijalankankannya.
The program consists of a group of branched command is often used in
programming. For example in determining the activities undertaken by a
system based on the age of a person who is diolahnya, let's say if age
concerned more than 18 years, it will be applied instructions
associated with age, assume a person is deemed to have
adults, while for other conditions are considered minors. Of the treatment
will be distinguished according to the systems that are running.
Superscalar organization in general
Superscalar design reasons
Most of the operations using the scale / This operation allows the scalar value
increase system performance until a certain level of Superscalar Implementation
The process of multiple instruction fetch simultaneously. Logic to determine
dependence which includes the actual value of the register mechanism for
communicate that value. Mechanism to initialize the instruction
parallel. Availability of resources for parallel execution of multiple instructions.
The mechanism of processing instructions in the order corresponding reply.
